PLL Phase Detector Error Calculator

✖Input reference clock phase is defined as a logic transition, which when applied to a clock pin on a synchronous element, captures data.ⓘ Input Reference Clock Phase [ΔΦ_in]			+10% -10%
✖Feedback clock pll is a pll that generates an output signal whose phase is related to the phase of an input signal.ⓘ Feedback Clock PLL [ΔΦ_c]			+10% -10%

✖PLL error detector is calculated when the phase error detector quantizes the phase difference between the up and down pulses.ⓘ PLL Phase Detector Error [ΔΦ_er]

⎘ Copy

👎

Formula

LaTeX

Reset

👍

Download CMOS Special Purpose Subsystem Formulas PDF PDF Image

PLL Phase Detector Error Solution

STEP 0: Pre-Calculation Summary

Formula Used

PLL Error Detector = Input Reference Clock Phase-Feedback Clock PLL
ΔΦ_er = ΔΦ_in-ΔΦ_c
This formula uses 3 Variables

Variables Used

PLL Error Detector - PLL error detector is calculated when the phase error detector quantizes the phase difference between the up and down pulses.
Input Reference Clock Phase - Input reference clock phase is defined as a logic transition, which when applied to a clock pin on a synchronous element, captures data.
Feedback Clock PLL - Feedback clock pll is a pll that generates an output signal whose phase is related to the phase of an input signal.

STEP 1: Convert Input(s) to Base Unit

Input Reference Clock Phase: 5.99 --> No Conversion Required
Feedback Clock PLL: 1.21 --> No Conversion Required

STEP 2: Evaluate Formula

Substituting Input Values in Formula

ΔΦ_er = ΔΦ_in-ΔΦ_c --> 5.99-1.21

Evaluating ... ...

ΔΦ_er = 4.78

STEP 3: Convert Result to Output's Unit

4.78 --> No Conversion Required

FINAL ANSWER

4.78 <-- PLL Error Detector

(Calculation completed in 00.004 seconds)

You are here -

Home » Engineering » Electronics » CMOS Design and Applications » CMOS Special Purpose Subsystem » PLL Phase Detector Error

Credits

Created by Shobhit Dimri

Bipin Tripathi Kumaon Institute of Technology (BTKIT), Dwarahat

Shobhit Dimri has created this Calculator and 900+ more calculators!

Verified by Urvi Rathod

Vishwakarma Government Engineering College (VGEC), Ahmedabad

Urvi Rathod has verified this Calculator and 1900+ more calculators!

< CMOS Special Purpose Subsystem Calculators

Capacitance of External Load

LaTeX Go Capacitance of External Load = Fanout*Input Capacitance

Fanout of Gate

LaTeX Go Fanout = Stage Effort/Logical Effort

Stage Effort

LaTeX Go Stage Effort = Fanout*Logical Effort

Gate Delay

LaTeX Go Gate Delay = 2^(N Bit SRAM)

PLL Phase Detector Error Formula

LaTeX Go

PLL Error Detector = Input Reference Clock Phase-Feedback Clock PLL
ΔΦ_er = ΔΦ_in-ΔΦ_c

What is PLL?

A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. There are several different types; the simplest is an electronic circuit consisting of a variable frequency oscillator and a phase detector in a feedback loop.

How to Calculate PLL Phase Detector Error?

PLL Phase Detector Error calculator uses PLL Error Detector = Input Reference Clock Phase-Feedback Clock PLL to calculate the PLL Error Detector, The PLL Phase Detector Error formula is defined as the phase difference between two clocks and is converted into 4-bit digital code, to increase the supply current of the charge pump. Phase error detector quantizes the phase difference between the Up and Dn pulses. PLL Error Detector is denoted by ΔΦ_er symbol.

How to calculate PLL Phase Detector Error using this online calculator? To use this online calculator for PLL Phase Detector Error, enter Input Reference Clock Phase (ΔΦ_in) & Feedback Clock PLL (ΔΦ_c) and hit the calculate button. Here is how the PLL Phase Detector Error calculation can be explained with given input values -> 4.78 = 5.99-1.21.

FAQ

What is PLL Phase Detector Error?

The PLL Phase Detector Error formula is defined as the phase difference between two clocks and is converted into 4-bit digital code, to increase the supply current of the charge pump. Phase error detector quantizes the phase difference between the Up and Dn pulses and is represented as ΔΦ_er = ΔΦ_in-ΔΦ_c or PLL Error Detector = Input Reference Clock Phase-Feedback Clock PLL. Input reference clock phase is defined as a logic transition, which when applied to a clock pin on a synchronous element, captures data & Feedback clock pll is a pll that generates an output signal whose phase is related to the phase of an input signal.

How to calculate PLL Phase Detector Error?

The PLL Phase Detector Error formula is defined as the phase difference between two clocks and is converted into 4-bit digital code, to increase the supply current of the charge pump. Phase error detector quantizes the phase difference between the Up and Dn pulses is calculated using PLL Error Detector = Input Reference Clock Phase-Feedback Clock PLL. To calculate PLL Phase Detector Error, you need Input Reference Clock Phase (ΔΦ_in) & Feedback Clock PLL (ΔΦ_c). With our tool, you need to enter the respective value for Input Reference Clock Phase & Feedback Clock PLL and hit the calculate button. You can also select the units (if any) for Input(s) and the Output as well.

Home

FREE PDFs

🔍 Search